TRICONEX 8306A Power module

Input Buffers, Analog Multiplexers, a Programmable Amplifier and a 16-bit A/D Converter digitize the analog input channels. The digitized values are stored in a dual-ported data buffer for access from the VMEbus. Optional low pass input filters minimize the effects of system noise and eliminate high frequency signal components which would otherwise cause accuracy problems. Input Buffers eliminate the error associated with varying source resistance. The scan rate is selectable from 381 Hz to 100 kHz for high-performance mode, and 381 Hz to 50 kHz for standard performance mode according to the scan rate equations in the Rate Control Register (RCR) on page 64. Operating modes are described in detail in Operating Modes on page 75. Regulated ±15 VDC power for the analog networks is obtained from the 5 VDC bus through a DC-to-DC Converter.

A separate gain buffer permits 

the input gain of each channel to be assigned individually. Gain codes ($0 = x1, $1 = x10) are first loaded into the gain buffer from the bus, and the gain for each channel is then used during the scanning process. A fixed gain for all channels can also be software programmed if programmable gain per channel is not required. Control signals and data transfers take place through the VMEbus P1 and P2 connectors. VMEbus Interface Logic controls data transfers through the P1 and P2 interface, and latches the operating mode parameters. Status monitoring and sequence timing are supported by a Bus Interrupter and Programmable Timer, both of which are controlled from the bus. Scan timing logic controls the analog input scanning process, uses the gain buffer to adjust input gain, sets the sampling rate, and routes digitized channel data to the data buffer

Board Selection

 VMEbus data transfer requests are accepted when the Board-Selection Comparator detects a match between the on-board selection jumpers shown in Figure 1-1 on page 21, and the address and address modifier lines from the backplane. When a match is detected, the board responds with a data transfer, after which the open collector DTACK interface signal is asserted (LOW). DTACK returns to the negated (HIGH) state when the transfer has been completed. During an interrupt response, DTACK is provided by the interrupt controller

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