ABB SPHSS13 Embedded module

Programmable address jumpers permit the VMIVME-3122 to be located in either the short I/O (A16) space, the standard address (A24) space, or the extended address (A32) space. The board can be located on any 2048-word boundary. Access privilege is jumper-designated as supervisory, non privileged, or either supervisory or non privileged. Data Transfers Data transfers respond to both D8 (EO) and D16 transfers. Any register or buffer location can be read at any time without affecting the existing scanning sequence.

The Analog-to-Digital Converter (ADC) will go through a calibration cycle on either a system reset or software reset. The user can initiate a calibration cycle by writing to location $000C. The data written to this location is arbitrary. If the automatic gain mode has been selected in the Configuration Control Register, channel gains other than x1 must be programmed as described in the “Gain RAM register” in the Programming Section.

Reset Operations and Initialization 

All Control Registers are reset by a VMEbus system reset. All control registers except the Interrupt Control Register (ICR) and Interrupt Vector Register (IVR) are reset by writing to location $000C. Either reset operation initializes the board to the following configurations: 1. Continuous scanning operating mode at 100 kHz rate for high-performance option and 50 kHz for standard performance option 

2. 64-channel block size (32 for 32-channel option, 16 for 16-channel option) 

3. 64-data word buffer size (32 for 32-channel option, 16 for 16-channel option) 

4. Automatic gain set to x1 

5. Offset binary data coding 

6. Self-test LED ON 

7. Data Ready flag at end-of-buffer

Conventions

 Hexadecimal Notation: To be consistent with conventional VMEbus development system nomenclature, hexadecimal numbers throughout this document are indicated with the prefix “$” unless otherwise indicated, and are expressed in byte “$XX”, word “$XXXX” or longword “$XXXX XXXX” formats. Decimal numbers are presented without a designating prefix. Logic States: This document uses the convention that a data bit or control line is “SET” when it is in the “1”, or HIGH state, and is “CLEARED” when “0” or LOW

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