TRICONEX 4328 Sequence control module

32b TMR - A logical 1 written to this bit location causes Interval Timer 1 and Interval Timer 0 to be configured as a 32-bit interval timer. A logical 0 written to this bit location enables only Interval Timer 0, providing a 16-bit interval counter. (Default is logic 0.) Bit 10: Flag - A logical 1 written to this bit location causes the Data RDY flag to be activated at the middle of the data buffer. A logical 0 written to this location causes the Data RDY flag to be activated at the end of the data buffer. (Default is logic 0.) Bit 07: CAL CMPLT - This bit is read only. A logical 1 indicates that the ADC calibration is complete. This bit is cleared at the beginning of an ADC calibration sequence initiated by a VMEbus reset, or a Software Reset Command.

Control And Status Register Bit Definitions (Continued)

 Bit 06: Data RDY - This bit is read only. A logical 1 indicates that the scan is complete and the data buffer is ready to be read. This bit is cleared on any read access to addresses $0080 - $0FFE. Bit 05: Armed - This bit is read only. A logical 1 indicates that the current scan mode is armed. This is cleared by a valid trigger, a VMEbus reset, or a Software Reset Command. Bit 04: Triged - This bit is read only. A logical 1 indicates that a valid trigger has been received and the current scan mode is active. This bit is cleared by scan completion, a VMEbus reset, or a Software Reset Comman

Configuration Control Register Bit Definitions

 Bits 15 through 11: Bufc [4:0] - Buffer Configuration control bits. This field is used to configure the available buffer size/block size combinations. Bit 10: ISource - A logical 1 written to this bit location causes a VMEbus interrupt request, when enabled, to be generated by the Data Counter. This allows an interrupt request to be generated when a programmed number of conversions have been completed. A logical 0 written to this location causes a VMEbus interrupt request, when enabled, to be generated by the Data RDY flag. This allows an interrupt request to be generated at the middle or the end of the data buffer. (Default is logic 0.)

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