ABB DSDI454 DSDI 454 Channel output module

The current count of timers 1 & 2 may be read via the Timer 1 & 2 Current Count Register (TMRCCR12), located at offset 0x20 from the address in BAR2. The mapping of bits in this register are as follows: When either field is read, the current count value is latched and returned. There are two modes that determine how the count is latched depending on the setting of the “Read Latch Select” bit in the WDT Control Status Register (CSR2). See the CSR2 register description for more information on these two modes.When this field is read, the current count value is latched and returned. There are two modes that determine how the count is latched depending on the setting of the “Read Latch Select” bit in the WDT Control Status Register (CSR2). See the CSR2 register description for more information on these two modes.

Timer 4 Current Count Register (TMRCCR4) 

The current count of Timer 4 may be read via the Timer 4 Current Count Register (TMRCCR4), located at offset 0x28 from the address in BAR2. The mapping of bits in this register are as follows: When this field is read, the current count value is latched and returned. There are two modes that determine how the count is latched depending on the setting of the “Read Latch Select” bit in the WDT Control Status Register (CSR2). See the CSR2 register description for more information on these two modes.

Timer 1 IRQ Clear (T1IC)

 The Timer 1 IRQ Clear (T1IC) register is used to clear an interrupt caused by Timer 1. Writing to this register, located at offset 0x30 from the address in BAR2, causes the interrupt from Timer 1 to be cleared. This can also be done by writing a “0” to the appropriate “Timer x Caused IRQ” field of the timer Control Status Register (CSR1). This register is write only and the data written is irrelevant.

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