ABB SDCS-PIN-52 3BSE011316R1 Analog output module

The REFCLK input buffer accepts any differential signal with a peak-to-peak differential amplitude of greater than 100 mV (for example, LVPECL or LVDS) or a standard single-ended low voltage TTL input, providing maximum system flexibility. Phase noise and duty cycle of the reference clock are not critical and 100 ppm accuracy is sufficient.The two uses of the reference clock are mutually exclusive. The reference clock can be used either as an acquisition aid for the ADN2816 to lock onto data or to measure the frequency of the incoming data to within 0.01%. (There is the capability to measure the data rate to approximately ±10% without the use of a reference clock.) The modes are mutually exclusive because, in the first use, the user knows exactly what the data rate is and wants to force the part to lock onto only that data rate; in the second use, the user does not know what the data rate is and wants to measure it.

Using the Reference Clock to Lock onto Data

 In this mode, the ADN2816 locks onto a frequency derived from the reference clock according to Data Rate/2CTRLA[5:2] = REFCLK/2CTRLA[7:6] The user must know exactly what the data rate is and provide a reference clock that is a function of this rate. The ADN2816 can still be used as a continuous rate device in this configuration, provided that the user has the ability to provide a reference clock that has a variable frequency (see Application Note AN-632).

Lock-to-reference mode is enabled by writing a 1 to I2 C Register Bit CTRLA[0]. Fine data rate readback mode is enabled by writing a 1 to I2 C Register Bit CTRLA[1]. Writing a 1 to both of these bits at the same time causes an indeterminate state and is not supported.

The reference clock 

can be anywhere between 10 MHz and 160 MHz. By default, the ADN2816 expects a reference clock of between 10 MHz and 20 MHz. If it is between 20 MHz and 40 MHz, 40 MHz and 80 MHz, or 80 MHz and 160 MHz, the user needs to configure the ADN2816 to use the correct reference frequency range by setting two bits of the CTRLA register, CTRLA[7:6].

Company introduction

Temporal Ming sheng automation equipment co., LTD. Was established in April 02, 2021, registered jiujiang ruichang city in jiangxi province, east yi road no. 23 lake farmers 401 mall, the legal representative person Zhou Zuochen.

[Main Products]

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