XYCOM XVME-682 Axial displacement module

These two FPP units share the same 4Kx16 bits OTP program memory, 208 bytes data SRAM and all the IO ports, these two FPP units are operated at mutual exclusive clock cycles to avoid interference. One task switch is built inside the chip to decide which FPP unit should be active for the corresponding cycle. The hardware diagram and basic timing diagram of FPP units are illustrated in Fig. 1. For FPP0 unit, its program will be executed in sequence every other system clock, shown as (M-1)th, Mth and (M+1)th instructions. For FPP1 unit, its program will be also executed in sequence every other system clock, shown as (N-1)th, Nth and (N+1)th instructions.

Hardware and Timing Diagram of FPP unit 

Each FPP unit has half computing power of whole system; for example, FPP0 and FPP1will be operated at 4MHz if system clock is 8MHz. The FPP unit can be enabled or disabled by programming the FPP unit Enable Register, only FPP0 is enabled after power-on reset. The system initialization will be started from FPP0 and FPP1 unit can be enabled by user’s program if necessary. Both FPP0 and FPP1 can be enabled or disabled by using any one FPP unit.

Program Counter 

Program Counter (PC) is the unit that contains the address of an instruction to be executed next. The program counter is automatically incremented at each instruction cycle so that instructions are retrieved sequentially from the program memory. Certain instructions, such as branches and subroutine calls, interrupt the sequence by placing a new value in the program counter. The bit length of the program counter is 12 for PMC234/PMS234. The program counter of FPP0 is 0 after hardware reset and 1 for FPP1. Whenever an interrupt happens in FPP0, the program counter will jump to 0x10 for interrupt service routine. Each FPP unit has its own program counter to control the program execution sequence.

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