Every interrupt request line has its own corresponding interrupt control bit to enable or disable it; the hardware diagram of interrupt function is shown as Fig. 14. All the interrupt request flags are set by hardware and cleared by writing intrq register. When the request flags are set, it can be rising edge, falling edge or both, depending on the setting of register integs. All the interrupt request lines are also controlled by engint instruction (enable global interrupt) to enable interrupt operation and disgint instruction (disable global interrupt) to disable it. Only FPP0 can accept the interrupt request, other FPP unit will not be interfered by interrupt.
The stack memory for interrupt is shared
with data memory and its address is specified by stack register sp. Since the program counter is 16 bits width, the bit 0 of stack register sp should be kept 0. Moreover, user can use pushaf / popaf instructions to store or restore the values of ACC and flag register to / from stack memory. Since the stack memory is shared with data memory, user should manipulate the memory using carefully. By adjusting the memory location of stack point, the depth of stack pointer for every FPP unit could be fully specified by user to achieve maximum flexibility of system.
Once the interrupt occurs
its operation will be: The program counter will be stored automatically to the stack memory specified by register sp.
New sp will be updated to sp+2.
Global interrupt will be disabled automatically.
The next instruction will be fetched from address 0x10. During the interrupt service routine, the interrupt source can be determined by reading the intrq register.
Application industry
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