MOTOROLA MVME135-1 Input logic module

This parasitic capacitance per pin is quite small (4 – 8 pF/pin) and will vary among HBM simulators. Since each floating pin is placed in parallel, the parasitic capacitance grows as the number of supply pins connected to the power plane increases. This tester parasitic capacitance will be in parallel with the test board capacitance and will have the affect of slowing down the HBM peak current rise time and will reduce the HBM peak currents. All relay matrix HBM simulators have this property.

The impact on HBM test

results is difficult to determine as it depends on the sensitivity of the ESD circuits of the supply pins to slow di/dt rise times. For some designs and equipment, the HBM levels may either increase or decrease. If failure levels are lower than expected, the best option is to retest the supply pins on a 2-pin manual tester. If the 2-pin HBM levels are much higher,then the open-relay capacitance is probably causing the lower HBM failure levels. In some cases, tester channels can be isolated by adding insulators or removing pogo pins from the HBM tester. This effectively “floats” the parallel supply pins. If there is a known problem for a given package, then special test fixture boards can be designed that connect only one supply pin from the socket to the HBM simulator. This modified test fixture board will not wire the floating pins to the HBM simulator, so these pins will not be able to charge up the open-relay capacitors. Another alternative method that can be used to overcome possible tester parasitic capacitance is the use of the “Alternative Pin Stress Method for Non-Supply Pins” discussed in Section 6.6.

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