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GE IS2020LNPSG3A Logic control module

GE IS2020LNPSG3A Logic control module

GE IS2020LNPSG3A Logic control module

This chapter describes setting parameters associated with the velocity and position loops. In some cases the user must adjust control loop parameters due to large mismatches between motor and load inertia, mechanical resonance, backlash, etc. This chapter provides guidance for handling these situations. Refer to Appendix A Selecting Motor Control Functionality for a description of the control loop architecture and control loop block diagrams. NOTE The two anti-resonant zeroes (ARZ0 and ARZ1) are assumed to both be off (set to zero) for this discussion.

VELOCITY LOOP 

The velocity loop block diagram is shown in Figure 2 in Appendix A. Velocity loop bandwidth is the key indicator of system performance. Systems with fast settling time must have high velocity loop bandwidth. Conversely, if the velocity loop bandwidth is low, attempting to achieve fast settling time by increasing the position loop bandwidth, KPP, leads to overshoot and ringing.

                                  

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