ABB BRC-100 P-HC-BRC-10000000 bridge controller

ABB BRC-100 P-HC-BRC-10000000 bridge controller

After debugger initialization is done and none of the above situations have occurred, the SYSFAIL* line is negated. This indicates to the user or VMEbus masters the state of the debugger. In a multi-computer configuration, other VMEbus masters could view the pertinent control and status registers to determine which CPU is asserting SYSFAIL*. SYSFAIL* assertion/negation is also affected by the ENV command. Refer to Appendix A. MPU Clock Speed Calculation The clock speed of the microprocessor is calculated and checked against a user definable parameter housed in NVRAM (refer to the CNFG command in Appendix A). If the check fails, a warning message is displayed. The calculated clock speed is also checked against known clock speeds and tolerances

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