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ABB NLIM02 Loop interface module

ABB NLIM02 Loop interface module

ABB NLIM02 Loop interface module


ABB NLIM02 Loop interface module

Master Address Translation Select #4 00000000 This register defines which bits of the address are significant. A logical one "1" indicates significant address bits, logical zero "0" is non-significant. Default is 0. Master Control #4 00 Defines the access characteristics for the address space defined with this master address decoder. Default is $00.Short I/O (VMEbus A16) Enable [Y/N] Y Yes, Enable the Short I/O Address Decoder. Short I/O (VMEbus A16) Control 01 Defines the access characteristics for the address space defined with the Short I/O address decoder. Default is $01. F-Page (VMEbus A24) Enable [Y/N] Y Yes, Enable the F-Page Address Decoder.

                                                                        

Company advantages

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