ABB 1SAP111100R0170 TB511-ETH B1 Terminal base

ABB 1SAP111100R0170 TB511-ETH B1 Terminal base

Figure 2-19 shows the timing requirements on the SERCLK and SERDATIN signals. These requirements must be observed for all communications. Tdelay is a SCXI-1140 specification. Tlow Thigh SERCLK SERDATIN SERDATOUT Tsetup Thold Tdelay Tlow Minimum low time 65 nsec minimum Thigh Minimum high time 400 nsec minimum Tsetup SERDATIN setup time 200 nsec minimum Thold SERDATIN hold time 200 nsec minimum Tdelay SERDATOUT delay 350 nsec maximum After the Slot-Select line to an SCXI-1140 has been asserted, you can write to its Configuration Register and read its Module ID Register by using the protocols of the following. After the 32 bits of data are read from the Module ID Register, further data will be zeros until reinitialization occurs. Deassert Slot-Select to reinitialize the contents of the Module ID Register.

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