GESPAC GESVIG-4VME output module

GESPAC GESVIG-4VME output module

When this bit is set to one, it has no effect. 5 RD Read – When cleared to zero, prevents the FIFO from being read. When set to one, the FIFO is read except at the end of a scan list entry during scanning, when reading is briefly disabled to advance to the next entry. 4 ONCE Once – When set to one, this bit shuts down the hardscan circuitry at the end of the scan list during a data acquisition. When cleared to zero, the circuitry wraps around and continues seamlessly with the first scan list entry after the entry is finished.Hardscan Reset – When cleared to zero, this bit resets the FIFO and all the hardware scanning circuitry to the power up state. When set to one, this bit has no effect.

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