HP 85309A Multi-channel controller

HP 85309A Multi-channel controller

HP 85309A Multi-channel controller

PCI Device Interrupt Map The PCI bus-based external devices include the PMC sites, Ethernet controller and the PCI-to-VME bridge. The default BIOS maps these external devices to the PCI Interrupt Request (PIRQx) lines of the ICH2. This mapping is illustrated in Figure 2-1 on page 47 and is defined in Table 2-5. The device PCI interrupt lines (INTA through INTD) that are present on each device cannot be modified. The PCI-to-VME Bridge has the capability of generating a Non-Maskable Interrupt (NMI) via the PCI SERR# line. Table 2-6 describes the register bits that are used by the NMI. The SERR interrupt is routed through logic back to the NMI input line on the CPU. The CPU reads the NMI Status Control register to determine the NMI source (bits set to 1). After the NMI interrupt routine processes the interrupt, software clears the NMI status bits by setting the corresponding enable/disable bit to 1. The NMI Enable and Real-Time Clock register can mask the NMI signal and disable/enable all NMI sources.

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