Agilent 37718A Communication performance analyzer

Agilent 37718A Communication performance analyzer

Agilent 37718A Communication performance analyzer

Timer Control Status Register 2 (TCSR2) The timers are also controlled by bits in the Timer Control Status Register 2 (TCSR2) located at offset 0x04 from the address in BAR2. The mapping of the bits in this register are as follows: The “Read Latch Select” bit is used to select the latching mode of the programmable timers (See “Timers” section above). If this bit is set to “0”, then each timer output is latched upon a read of any one of its address. For example, a read to the TMRCCR12 register latches the count of timers 1 and 2. A read to the TMRCCR3 register latches the count of timer 3. This continues for every read to any one of these registers. As a  Read Latch Select TCSR2[0] R/W Reserved All Other Bits R/W

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