Agilent 83620A Synthetic frequency sweeper

Agilent 83620A Synthetic frequency sweeper

Agilent 83620A Synthetic frequency sweeper

VME Control The following table shows the register definitions for the VMIVME-7750 (offset from BAR0). Bit Name Bit Definition MEC_SEL 0 Master big-endian enable bit 1=Big Endian 0=Little Endian bit SEC_SEL 1 Slave Big-Endian enable bit 1=Big Endian 0=Little Endian ABLE 2 Auxiliary BERR logic enable bit 1=Aux. BERR enabled 0=Aux. BERR disabled BTO 3 Bus error timer enabled 1=enabled 0=disabled BTOV [1:0] 5:4 Timeout value 00 - 16uS 01 - 64uS 10 -256uS 11 - 1.00mS BERRI 6 BERR interrupt enable 1=Interrupt enabled 0=Interrupt disabled BERRST 7 BERR status read/clear bit 1=Clear BERR status 0=Do nothing SFENA 8 Enables generation of VME SYSFAIL upon WDT timeout 1= Enable SYSFAIL generation 0=Disable

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