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ABB DSRF182AK02 3BSE014078R1 framework

ABB DSRF182AK02 3BSE014078R1 framework

ABB DSRF182AK02 3BSE014078R1 framework

The maximum pulse current, deliverable by the device can be adjusted with the potentiometer P2 of the internal current limiting. This current limiting is connected on load side of the previously mentioned current limitations - this guarantees that the current adjusted here, can never by exceeded.

Current-mode control and current controller 

As shown in the block diagram, the current-mode control must be passed through first, to form the actual current set value for the current controller of the U-conductor current and of the V-conductor current. The nominal current of the speed controller output (conductor current) is converted, depending on signals of the resolver, in two current set values with an offset of 120º and fed to the current controllers for the phases U and V. The nominal current of the third phase W is imitated by subtraction at the outputs of the current controller. This guarantees, that the sum of the currents is always zero. The pulse-width modulator generates from the three d.c. voltage signals for the conductor currents six PWM signals, which serve for activating the driver stage after the creation of the lag time.

                                  

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