ebm W2S130-AA01-16 FAN

Detailed

ebm W2S130-AA01-16 FAN

W2S130-AA01-16 contains the Interval Timer and Channel Counter. Two of the counter sections are driven from a 6.25 MHz clock, and can be cascaded as a 32- bit timer for delays up to 687 seconds. Timed data acquisition bursts occur at the interval programmed into the Interval Timer. The channel counter can be programmed to generate an interrupt after a programmed number of data buffer locations have been updated, or can be read directly to serve as a data pointer.

VMEbus data transfer requests are accepted when the Board-Selection Comparator detects a match between the on-board selection jumpers shown in Figure 1-1 on page 21, and the address and address modifier lines from the backplane. When a match is detected, the board responds with a data transfer, after which the open collector DTACK interface signal is asserted (LOW). DTACK returns to the negated (HIGH) state when the transfer has been completed. During an interrupt response, DTACK is provided by the interrupt controller.

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