ABB CI853K01 3BSE018103R1 gateway module

Detailed

ABB CI853K01 3BSE018103R1 gateway module

All Control Registers are reset by a CI853K01 3BSE018103R1 system reset. All control registers except the Interrupt Control Register (ICR) and Interrupt Vector Register (IVR) are reset by writing to location $000C. Either reset operation initializes the board to the following configurations: 1. Continuous scanning operating mode at 100 kHz rate for high-performance option and 50 kHz for standard performance option 2. 64-channel block size (32 for 32-channel option, 16 for 16-channel option) 3. 64-data word buffer size (32 for 32-channel option, 16 for 16-channel option) 4. Automatic gain set to x1 5. Offset binary data coding 6. Self-test LED ON 7. Data Ready flag at end-of-buffer The Analog-to-Digital Converter (ADC) will go through a calibration cycle on either a system reset or software reset. The user can initiate a calibration cycle by writing to location $000C. The data written to this location is arbitrary. If the automatic gain mode has been selected in the Configuration Control Register, channel gains other than x1 must be programmed as described in the “Gain RAM register” in the Programming Section.

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