Detailed
ABB RDCO-03C Axial displacement module
The transfer of data between nodes is software transparent, so no I/O overhead is required. Transmit and Receive FIFOs buffer data during peak data rates to optimize CPU and bus performance to maintain high data throughput. The Reflective Memory also allows interrupts to one or more nodes by writing to a byte register. These interrupt (three levels, each user definable) signals may be used to synchronize a system process, or used to follow any data. The interrupt always follows the data to ensure the reception of the data before the interrupt is acknowledged. The RDCO-03C requires no initialization unless interrupts are being used. If interrupts are used, vectors and interrupt levels must be written to on-board registers and the interrupts enabled.
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