ABB AGPS-21C Logic module

ABB AGPS-21C Logic module

AGPS-21C input channels are selected with CSR bits D00 through D04, shown in Figure 3.5-1 as MUX A0 H through MUX A04 H. In order to test the four input multiplexers dedicated to P2 inputs, channels 00, 04, 08, and 12 are routed through the self-test multiplexer. The P2 multiplexers are selected when the CSR D07 control bit is cleared LOW. Buffered low pass filters, shown in Figure 3.6-1, are available options for all P2 analog inputs. Since the filters are buffered before the multiplexer, the throughput is not restricted by reflected multiplexer currents. Application programs, therefore, can realize the maximum sample rates permitted by the ADC timing controller.

After passing through the input multiplexers, the analog input signals are routed to analog configuration networks for final switching into the ADC channel. To test the input multiplexers, four of the analog channels (one for each multiplexer device) are first switched through the self-test multiplexer shown in Figure 3.7-1.

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FOXBORO FBM230 P0926GU

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