ABB SPAJ142C Monitor module

ABB SPAJ142C Monitor module

The SPAJ142C may be programmed to respond to an external TTL active low or "zero" pulse. For external trigger operation, the user programs the channel, mode and Start Settling H bits of the CSR. Do not set the Enable Start Convert H bit D12 of the CSR, instead set the Enable External Trigger H bit D15 of the CSR to a "one." An external logic level "zero" trigger pulse of a least 100 ns may then be input to the board via the P2 connector pin A28. On the board, this input pin for external trigger is pulled high through a 4.7 k resistor to +5 V. The active low pulse will initiate a single A/D conversion. At the completion of the conversion, the new data ready flag will be set high. In addition to enabling the External Trigger operation in the CSR, jumpers J41 and J42 must be configured. J41 must be omitted. J42 pin 1 should be connected to J42 pin 2, which connects the external trigger return (P2 pin C28) to the board ground. For location of the jumpers, refer to Section 5, Figure 5.4-1.

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