ABB YPO105E YT204001-FR Serial Link Module

ABB YPO105E YT204001-FR Serial Link Module

The YPO105E YT204001-FR Board is designed with address decode logic that allows the user to select a board jumper address within the short I/O memory address map. An 8-bit DIP switch is designed to provide inputs to the address comparator as shown in Figure 2-2 on page 22. A comparison is made with address bits A08 through A15. A jumper (AM) is provided, as shown in Figure 2-2, that gives the user the option of selecting short supervisory or nonprivileged I/O transfers. The eight least significant bits (LSBs) of address (A01 through A07) are used by the YPO105E YT204001-FR for internal I/O register transfers.

The YPO105E YT204001-FR foundation logic consists primarily of an 8-bit data I/O buffer, a control signal buffer, a DTACK generator and a BIM. Additional logic is provided to generate the clock signals for the MK68564 SIO integrated circuit. A functional block diagram of the foundation logic is shown in Figure 2-3 on page 26.

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