ABB YPO106A YT204001-EG Serial Link Controller

ABB YPO106A YT204001-EG Serial Link Controller

A detailed functional block diagram of the interrupt logic is shown in Figure 2-4 on page 27. The YPO106A YT204001-EG is designed with Epic’s Ei68C153 BIM. Only two of the four channels available on Ei68C153 are used by the YPO106A YT204001-EG. Channel 3 of the BIM is used for serial Channels 0 and 1, and Channel 2 of the BIM is used for serial Channels 2 and 3. 

The MK68564 SIO integrated circuit is designed to operate as an independent, interrupting "peripheral". It contains an Internal Vector Register (IVR); therefore, the Ei68C153 must be programmed so that it will not generate vector data and DTACK. The Vector Register within the MK68564 is different from the other 24 registers within the SIO chip, because it may be accessed through either Channel "A" or Channel "B" of the SIO during an R/W cycle. During an interrupt acknowledge cycle, the contents of the Vector Register are passed to the VMEbus to be used as a pointer to an interrupt service routine. If the status affects vector bit is low in the Interrupt Control Register (ICR) any data written to the Vector Register will be returned unmodified during a read cycle or an IACK cycle.

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