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ABB PMKHRMBRC3000B Redundant channel card

ABB PMKHRMBRC3000B Redundant channel card

ABB PMKHRMBRC3000B Redundant channel card

The PMKHRMBRC3000B Board VMEbus foundation logic, shown in Figure 1-3 below, consists primarily of a DTACK generator, control signal buffers, and data transceivers. These transceivers buffer data to be transmitted to the output registers and to the Control and Status Register (CSR), which controls the front panel Fail LED and output isolation switches. The control logic is designed to support 8- and 16-bit transfers. Address bits A01 and A02 are decoded to select one of two output data registers and the CSR.
A functional block diagram of the address decode logic is shown in Figure 1-2 below. Two eight-position "DIP" switches are provided to enable the user to select from a wide range of short I/O memory addresses for the board address. The user may also select nonprivileged or supervisory short I/O transfers. The board is configured at the factory to respond to short supervisory I/O transfers.


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